1. Field of the Invention
The present invention relates to methods for fabricating packaging substrates, and more particularly, to a method for fabricating packaging substrates for avoiding a waste of materials resulting from discarding a temporary carrier during the fabricating process of packaging substrates.
2. Description of Related Art
Electronic products are increasingly multifunction and high-performance devices. In order to fulfill the packaging requirements for a high degree of integration and miniaturization of semiconductor packages such that more active/inactive components and circuit connections can be provided, the semiconductor packaging substrate has evolved from a double-layer board to a multi-layer board to increase available wiring layout area in the semiconductor packaging substrate by using interlayer connection techniques in a limited space, such that the requirement for a high-density integrated circuit can be accommodated, while lowering the thickness of the packaging substrate to achieve the goal of making the package unit light in weight, physically small, and with increased electrical functionality.
In the prior art, a multi-layer board is comprised of a core plate and wiring built-up structures formed on both sides thereof. However, using the core plate results in increasing the conducting trace length and overall thickness of the structure, which makes it very hard to accommodate the requirement of compact size while increasing the functionality for an electronic product.
As such, a coreless board structure has been developed in order to decrease the conducting trace length and to lower the overall structural thickness, and to accommodate the trend of compact, dense, high-frequency products. FIGS. 1A to 1F show cross-sectional views of a packaging substrate and a fabrication method thereof in a prior art.
Referring to FIG. 1A, a carrier plate 10 has two opposite sides, on which respectively two thin-film metal layers 11, two release films 12, and two carrier metal layers 13 are disposed in sequence.
Referring to FIG. 1B, a first dielectric layer 14 is formed on the carrier metal layers 13.
Referring to FIG. 1C, a plurality of vias 140 are formed in the first dielectric layers 14 by photolithography or laser ablation, and subsequently a plurality of depressions 130 are formed on the surfaces of the carrier metal layers 13 exposed by the vias 140.
Referring to FIG. 1D, solder bumps 141a and first conductive vias 141b are formed in sequence in the depressions 130 and the corresponding vias 140, and first wiring layers 142 are formed on the first dielectric layers 14, the first wiring layers 142 electrically connecting with the first conductive vias 141b. Subsequently, two built-up structures 15 are formed on the first dielectric layers 14 and the first wiring layers 142, each built-up structures 15 being comprised of at least one second dielectric layer 151, a second wiring layer 152 disposed on the second dielectric layer 151, and a plurality of second conductive vias 153 disposed in the second dielectric layers 151 and electrically connecting the first wiring layer 142 and the second wiring layer 152. The outmost second wiring layers 152 of the built-up structures 15 further have a plurality of conductive pads 154. Insulating protective layers 16 are formed on the outmost layers of the built-up structures 15. The insulating protective layers 16 have a plurality of insulating protective layer openings 160 formed therein from which the conductive pads 154 are exposed, respectively.
Referring to FIG. 1E, the carrier metal layers 13 are separated by the release films 12 to obtain two initial packaging substrates 1 separated from the carrier plate 10.
Referring to FIG. 1F, the carrier metal layer 13 is removed to form a plurality of solder bumps 141a protruding from the surface of the first dielectric layer 14 to obtain a packaging substrate, such that the solder bumps 141a can provide for subsequently mounting the semiconductor chip (not shown).
As mentioned above, in the prior art method for fabricating a packaging substrate, a release film 12 is formed on the both sides of the carrier plate 10, respectively, wherein thin-film metal layers 11 are sandwiched between each release film 12 and the carrier plate 10; then built-up structures 15 are formed on the thin-film metal layers 11 of both sides of the aforementioned structure; and, finally, two packaging substrates are formed by separating the built-up structures on both sides along the interface of the release film 12 and the carrier metal layer 13.
However, in the prior art fabrication method, the thin-film metal layer 11 and the release film 12 have to be additionally formed on the both sides of the carrier plate 10 for temporarily supporting the structures on the both sides and providing for separation, and, in the end, the temporary carrier (including carrier plate 10, two thin-film metal layers 11 and two release films 12) will be discarded, which results in process complexity, material waste and increased manufacturing costs.
Therefore, in view of the above-described problems, it is highly desirable to find a way to avoid problems in the prior art such as discarding the temporary carrier that results in the material waste and process complexity and the like for manufacturing a packaging substrate.